Computer telephony is based on digital communication across time division multiplexed serial data lines, known as "streams." A typical computer telephony bus provides 16 or more streams, which each have between 32 and 128 timeslots. The timeslots in the streams all occur at the same time because the streams are synchronized with reference to a single bit called the "frame pulse."
Circuits that interface with the bus must also be synchronized to the clocks present on the bus to ensure that the data transferred between the circuit and the bus have the same frequency as the data on the bus. But frequency lock does not ensure that the timeslots in the bus are lined up with events in interface. In such a situation, the interface frame and the bus frame are considered to be "frequency locked, but not phase aligned."
Upon power-up and initialization of an entire system, an interface circuit that interfaces with the bus, such as a digital switch, will generally be both frequency locked and phase aligned. During the course of operation, however, it is possible for a new clock circuit to assume the role of "master," and take on the role of establishing the clocking and frame synchronization. When this happens, the circuit may remain frequency locked, relative to the new clock master but lose phase alignment. It is possible to reinitialize the circuit to again achieve synchronization, but this can take time and result in data loss.